1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a plurality of easily-controllable memory cells which can be accessed at high speed.
2. Description of the Prior Art
A conventional, standard, general-purpose DRAM has a page mode for access at a high speed cycle time. As is commonly known, in this page mode it is possible to access specified memory cells in a row of a memory cell array selected by means of a row address, by arbitrarily changing a column address in a string of simultaneously sensed memory cells.
High speed access is possible with this type of mode for the following reasons. Considerable time is required for sense amplification of the cell data in a DRAM, but once the data has been sensed, the read-out of this data proceeds very quickly. Once a column address has been changed in the page mode operation, the access to the sense amplifier which has sensed that cell is commenced and the data is output when a CAS signal is switched to xe2x80x9cL.xe2x80x9d Accordingly, the page mode is a random access mode.
Recently, the capacity of memory chips has been increasing, year after year. Accordingly, the number of chips used in a system has been more reduced. Therefore, when large volume chips are used in the prior art, namely when many chips are used in the system, these chips are divided into a number of groups which are interleaved, making it possible to construct and utilize a memory system in which the apparent cycle time is short, but this method cannot be used to a system having small volume chips.
On the other hand, the speed of an MPU has been increasing year after year, and even in a small scale system there is a strong necessity to achieve high speeds. For these reasons, it has become necessary for a memory to operate at even higher cycle speeds. Also, from these requirements it is not absolutely necessary for the access operation to be random; there are many cases in which all that is required is the ability to read or write a string of data at high speed.
A method for providing a high speed operation for RAM including SRAM and the like has been reported in the following literature.
Chikai Ohno, xe2x80x9cSelf-Timed RAM: STRAMxe2x80x9d, FUJITSU Sci. tech. J., 24, 4, pp293-300, December 1988.
In the literature, the following method is disclosed. A RAM (STRAM) operates in synchronization with a system clock, namely in the RAM, an address signal and R/W signals for a read-out or for write-in are received in synchronization with the clock signal at a timing, then at the next timing content of the memory cell addressed by the address signal is output.
However, in this method the address signal must be provided every cycle of the system clock. Therefore there is a disadvantage that the access operation to a memory cell in the RAM cannot be followed to the period of the system clock when the period becomes high.
When a conventional page mode is used an address change is absolutely necessary. Therefore, it is impossible to operate with a higher access cycle time which is more than the time determined by the address control of the system. Speed increases for the memory access operation are therefore limited.
Control signals such as RAS signals and CAS signals must be supplied to the memory chip. These control signals are produced by the system. Accordingly, the control for supplying the control signals to the memory chip is an obstacle to providing a high speed operation with a memory system which includes an access means. In this case, the operation control of the system becomes so complex that it is difficult to use the control of the system.
According to an aspect of the present invention, there is provided a semiconductor device comprising a memory cell array having a plurality of memory cells arranged in rows and columns, a counting section to which a clock signal is input, configured to count transition of the clock signal and determine first data of a plurality of data to be transferred sequentially, a control section configured to fetch information indicating a memory cell location in the memory cell array in response to a counting result of the counting section and control consecutive input and output of a plurality of data stored in the memory cell array every cycle of the clock signal, a specification section configured to decode the information fetched by the control section and designate a memory cell in the memory cell array, and a data input/output section configured to input data to the memory cell designated by the specification section and output data from the memory cell designated by the specification section, wherein input and output of the data are time-shared.
According to another aspect of the present invention, there is provided a method of accessing a semiconductor device that operates in synchronism with a clock signal, comprising fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plurality of data to be transferred sequentially, decoding the information indicating the memory cell location in the memory cell array and designating the memory cell, receiving data stored in the memory cell designated by the information indicating the memory cell location in the memory cell array in synchronism with the clock signal after a predetermined number of cycles of the clock signal, and outputting a plurality of data stored in the memory cells in synchronism with the clock signal and storing a plurality of input data in the memory cells in synchronism with the clock signal.